CV
My resume.
Contact Information
| Name | Yubin Qin (秦育彬) |
| Professional Title | Dr. |
| qinyb98@gmail.com | |
| Location | ByteDance, Pudong, Shanghai, Shanghai 201200 |
Please download the pdf CV with these two links:
📥 Download PDF: English Version | 中文版简历
Experience
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2026 - Present Shanghai, China
Engineer
ByteDance (字节跳动)
Working on AI chip and infrastructure.
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2020 - 2026 Beijing, China
Graduate Researcher
Tsinghua University (Laboratory)
Led multiple 22/28nm tape-outs and national-level research projects.
- Designed high-performance neural network computing IPs.
- Deployed in commercial chips with over 10 million units shipped.
Education
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2020 - 2026 Beijing, China
Ph.D.
Tsinghua University
Electronic Science and Technology
- Advised by Prof. Shouyi Yin.
- Research Focus: High-efficiency AI processors and architecture.
- Rank: Top 25%.
- 20+ Publications, 10+ international & domestic awards.
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2016 - 2020 Nanjing, China
B.Eng
Southeast University
Electronic Science and Technology
- Rank: 1/161.
- National Scholarship (Top 1%).
Awards
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2025 ISSCC Highlight Award
ISSCC
The only awarded team from the Far East for our work on AI chips.
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2025, 2024 Special-Class Scholarship Nomination
Tsinghua University
Two-time nominee for the highest student honor at Tsinghua University.
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2024 Deng Jiaxian Scholarship
Tsinghua University
Top 20 out of 46,000+ students.
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2024, 2018 National Scholarship
Ministry of Education, China
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2024 Research Excellence Award
School of Integrated Circuits, Tsinghua University
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2024 National Integrated Circuit Shortage Talent Scholarship
Ministry of Education
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2023 Top 10 Advances in China's Chip Science
CHIP Committee
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2023 Top 10 Research Advances in China's Semiconductor Industry (Nominee)
Journal of Semiconductors
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2020 Future Scholars Scholarship
Tsinghua University
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2020 Outstanding Graduate
Southeast University
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2019 Baosteel Excellent Student Award
Baosteel Education Foundation
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2019 President's Scholarship
Southeast University
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2017 Philips Scholarship
Southeast University / Philips Inc.
Publications
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2026 AMBER: A Unified Accelerator for Multi-Precision LLM Inference Exploiting Bit-Level Redundancy and Reconfigurability
ACM/IEEE Design Automation Conference (DAC)
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2026 MoBiLE: Efficient Mixture-of-Experts Inference on Consumer GPU with Mixture of Big Little Experts
Asia and South Pacific Design Automation Conference (ASP-DAC)
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2025 An 88.36TOPS/W Bit-Level-Weight-Compressed Large-Language-Model Accelerator with Cluster-Aligned INT-FP-GEMM and Bi-Dimensional Workflow Reformulation
IEEE International Solid-State Circuits Conference (ISSCC)
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2024 Ayaka: A Versatile Transformer Accelerator With Low-Rank Estimation and Heterogeneous Dataflow
IEEE Journal of Solid-State Circuits (JSSC)
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2024 MECLA: Memory-Compute-Efficient LLM Accelerator with Scaling Sub-matrix Partition
ACM/IEEE Annual International Symposium on Computer Architecture (ISCA)
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2024 A 52.01 TFLOPS/W Diffusion Model Processor with Inter-Time-Step Convolution-Attention-Redundancy Elimination and Bipolar Floating-Point Multiplication
IEEE Symposium on VLSI Technology and Circuits (VLSI)
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2023 A 28nm 49.7TOPS/W Sparse Transformer Processor with Random-Projection-Based Speculation, Multi-Stationary Dataflow, and Redundant Partial Product Elimination
IEEE Asian Solid-State Circuits Conference (A-SSCC)
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2023 FACT: FFN-Attention Co-optimized Transformer Architecture with Eager Correlation Prediction
ACM/IEEE Annual International Symposium on Computer Architecture (ISCA)
Skills
Architecture (Expert): GPGPU, LLM Accelerator, PIM, 3D IC, Wafer-scale AI
Engineering (Expert): Verilog, Chisel, C++, Python, UrsaSim Simulator, RTL Design
Languages
Chinese Mandarin : Native speaker
English : Professional working proficiency
Japanese : Daily communication