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qinyb98@gmail.com

(+86) 18260207071

Shanghai, China

I am Yubin Qin, an engineer at ByteDance. I received my Ph.D. from the School of Integrated Circuits at Tsinghua University, where I was advised by Prof. Shouyi Yin. Before coming to Tsinghua, I received my B.Eng. degree in Electronic Science and Technology from Southeast University in 2020, graduating with the highest GPA (3.9/4.0, Rank 1/161).

My research primarily focuses on high-performance AI architecture and chip design, targeting to explore the design philosophies and paradigms for next-generation AI chips and architectures. I am particularly interested in the algorithm-infra-chip design space exploration (DSE), seeking to break the traditional boundaries between layers to achieve unprecedented hardware efficiency. Currently, my goal is to architect high-performance AI computing infrastructures by leveraging emerging technologies—such as Processing-in-Memory (PIM), 3D integration, wafer-scale systems, etc.—to sustain the ever-scaling demands of future AI workloads.

I have published over 20 papers (8 as first author) in top venues like ISSCC, ISCA, JSSC, and VLSI. My research on LLM acceleration was honored as an ISSCC 2025 Highlight—the sole winner from the Far East in its session. I have completed multiple 22/28nm tape-outs and designed neural network IPs that are now deployed in over 10 million commercial chips.

Currently, I am an engineer at ByteDance, working on AI chip and infrastructure.

(Feel free to reach out via email for research discussions or collaborations!)

news

Jul 27, 2026 Our paper AMBER: A Unified Accelerator for Multi-Precision LLM Inference Exploiting Bit-Level Redundancy and Reconfigurability presented at DAC 2026 in Long Beach, CA.
Jul 01, 2026 Joined ByteDance as an AI chip engineer.
Jun 27, 2026 Graduated with a Ph.D. from Tsinghua University.

selected publications

  1. ISSCC
    An 88.36 TOPS/W Bit-Level-Weight-Compressed Large-Language-Model Accelerator with Cluster-Aligned INT-FP-GEMM and Bi-Dimensional Workflow Reformulation
    Yubin Qin, Yang Wang, Jiachen Wang, and 5 more authors
    In IEEE International Solid-State Circuits Conference (ISSCC), 2025
  2. ISCA
    MECLA: Memory-Compute-Efficient LLM Accelerator with Scaling Sub-matrix Partition
    Yubin Qin, Yang Wang, Zhiren Zhao, and 5 more authors
    In ACM/IEEE Annual International Symposium on Computer Architecture (ISCA), 2024
  3. VLSI
    A 52.01 TFLOPS/W Diffusion Model Processor with Inter-Time-Step Convolution-Attention-Redundancy Elimination and Bipolar Floating-Point Multiplication
    Yubin Qin, Yang Wang, Xiaolong Yang, and 4 more authors
    In IEEE Symposium on VLSI Technology and Circuits, 2024
  4. JSSC
    Ayaka: A Versatile Transformer Accelerator with Low-Rank Estimation and Heterogeneous Dataflow
    Yubin Qin, Yang Wang, Dazheng Deng, and 10 more authors
    IEEE Journal of Solid-State Circuits, 2024
  5. A-SSCC
    A 28nm 49.7 TOPS/W Sparse Transformer Processor with Random-Projection-Based Speculation, Multi-Stationary Dataflow, and Redundant Partial Product Elimination
    Yubin Qin, Yang Wang, Dazheng Deng, and 10 more authors
    In IEEE Asian Solid-State Circuits Conference (A-SSCC), 2023
  6. ISCA
    FACT: FFN-Attention Co-optimized Transformer Architecture with Eager Correlation Prediction
    Yubin Qin, Yang Wang, Dazheng Deng, and 6 more authors
    In ACM/IEEE Annual International Symposium on Computer Architecture (ISCA), 2023